1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a repair circuit for repairing defective memory cells.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device includes a normal cell array 110, a redundancy cell array 120, a comparison unit 130, a control unit 140, a normal decoder 150, and a redundancy decoder 160.
The normal cell array 110 includes a plurality of memory cells that are configured in a plurality of row lines (not shown) and a plurality of column lines, corresponding to a plurality of row addresses (not shown) and a plurality of column addresses CADD.
The redundancy cell array 120 includes a plurality of memory cells for replacing defective memory cells.
The normal cell array 110 includes normal column lines BL1 to BLN corresponding to a plurality of normal column signals, and the redundancy cell array 120 includes a plurality of redundancy column lines RBL1 to RBLM corresponding to a plurality of redundancy column signals.
The comparison unit 130 receives column addresses CADD and repair addresses YRA from an exterior (e.g. an exterior source of device). The repair addresses YRA may be received from a storage unit (not shown) that stores defect information. The comparison unit 130 may compare the column addresses CADD and the plurality of repair addresses YRA, and output comparison results as a plurality of column repair signals SYEB.
The control unit 140 receives the plurality of column repair signals SYEB. When even one of the plurality of column repair signals SYEB is activated, the control unit 140 activates a cut-off signal YIKILLB, meaning that the column addresses CADD applied from the exterior are defect addresses.
The normal decoder 150 receives the column addresses CADD, a test signal TDBLEYI, and the cut-off signal YIKILLB. The test signal TDBLEYI may be activated to perform a test operation by driving double column lines, not a single column line. When the cut-off signal YIKILLB is deactivated and the test signal TDBLEYI is activated, the normal decoder 150 ignores the most significant bit of the column addresses CADD, and decodes the received column addresses CADD to output decoded signals. The normal decoder 150 activates the normal column lines BL<1:N> corresponding to the decoded signals. The normal decoder 150 interrupts the decoding operation of the column addresses CADD when the cut-off signal YIKILLB is activated.
The redundancy decoder 160 receives and decodes the plurality of column repair signals SYEB, and activates the redundancy column lines RBL<1:M> of the redundancy cell array 120 in correspondence with the activated column repair signal SYEB.
Next, describing operations, the activated test signal TDBLEYI is inputted to the normal decoder 150 to perform the test operation by driving double column lines. By comparing the column addresses CADD and the repair addresses YRA, if it is determined as a comparison result that the column addresses CADD and the repair addresses YRA do not correspond to each other, the column repair signal SYEB is deactivated and, accordingly, the cut-off signal YIKILLB of the control unit 140 is deactivated. When the column addresses CADD and the test signal TDBLEYI are enabled, the normal decoder 150 ignores the most significant bit of the column addresses CADD, and decodes the received column addresses CADD to output decoded signals. The normal decoder 150 may activate the normal column lines BL<1:N> corresponding to the decoded signals. Since the normal decoder 150 ignores the most significant bit of the column addresses CADD in response to the test signal TDBLEYI, first and second normal column lines may be finally activated among the normal column lines BL<1:N>.
Conversely, if the column addresses CADD and the repair addresses YRA correspond to each other, the column repair signal SYEB is activated. The redundancy decoder 160 may receive and decode the column repair signals SYEB, and activate the redundancy column lines RBL<1:M> of the redundancy cell array 120 in correspondence with the activated column repair signal SYEB. The control unit 140 that receives the column repair signals SYEB generates the activated cut-off signal YIKILLB, and the normal decoder 150 interrupts the decoding operation in response to the cut-off signal YIKILLB. That is to say, even when the test signal TDBLEYI for a double column test mode is activated, the normal decoder 150 does not perform the decoding operation in response to the cut-off signal YIKILLB, and the normal column lines BL<1:N> are not activated.
Therefore, when the first normal column line corresponding to the column addresses CADD is not determined to be defective in the double column test mode, a test may be performed by simultaneously activating the first normal column line and the second normal column line, which have the same addresses, as the column addresses CADD, excluding its most significant bit. However, when the first normal column line is determined to be defective, a redundancy column line is activated through a repair operation, and the second normal column line is deactivated. In other words, in the double column test mode, if the first normal column line is determined to be defective and repaired between the first and second normal column lines, which have different addresses in terms of the most significant bit, a test may not be simultaneously performed for the remaining second normal column line.